Posted: January 29th, 2016

Combinational and Sequential Logic Design

Design a combinational circuit which produces a logic 1 output when the majority of bits of a four bit number are at logic 0.

Minimise the design using either boolean algebra of Karnaugh maps and design the minimised circuit using a combination of AND, OR and NOT gates.

Show how the circuit can be redsigned using NAND only logic

Simulate both circuits using Proteus and show graphically that the output meets the design requirements for both circuits.