Posted: September 18th, 2017
Digital Systems and Microprocessor Design
e) You are provided with the following partial dump of the memory connected to the educational processor. A program starts at address zero, but we do not know how large it is.
Decode the instructions from address 0 to 15 and write the corresponding program in assembler (if it is not possible to decode an instruction indicate “invalid opcode”).
Indicate where (memory address) the program stops (i.e. the processor stops performing any useful computation).
Explain line by line what the instructions do, and explain what the overall program does (hint: look at the register values).
00 10 03
02 11 04
04 42 02
06 55 00
08 B1 10
0A 22 00
0C 35 01
0E B0 06
10 B0 10
12 D0 55
14 47 37
f) We are interested in realising a processor with 8 registers instead of 4. Discuss the changes that would be required to the instruction encoding to realise such a processor. Explain what other changes the instruction encoding would lead to, and how this would affect on the functionality of the processor.
g) Write an assembler program that performs a loop exactly 5 times. Write down the assembler code first. Then, indicate which values must be stored at which memory locations (i.e. the instruction encoding) to realise this program. Assume the program starts at memory location 0 (i.e. on reset).
h) Consider the instruction “xor c,3Ah” (assume a=10,b=20,c=55,d=40). Assume we are shortly before the clock edge of the “execute” cycle.
By analyzing the VHDL code, explain what happens inside the educational processor to execute this instruction. Specifically, indicate the state of the following signals (or indicate if undefined):
instruction (in cpu.vhd)
rrd1 (port of cpuregbank in cpu.vhd)
rrd2 (port of cpuregbank in cpu.vhd)
rwr (port of cpuregbank in cpu.vhd)
d (port of cpuregbank in cpu.vhd)
reg1out (in cpu.vhd)
reg2out (in cpu.vhd)
source (in cpu.vhd)
regwren (in cpu.vhd)
ram_we (in cpu.vhd)
ram_address (in cpu.vhd)
ram_datawr (in cpu.vhd)
op (port of cpualu in cpu.vhd)
a (port of cpualu in cpu.vhd)
b (port of cpualu in cpu.vhd)
aluqout (in cpu.vhd)
wrdata (in cpu.vhd)
finally, summarize the overall processor behavior with this instruction.
i) Assume that a VHDL component “mul” is available that takes two 8-bit numbers A and B as input (i.e. STD_LOGIC_VECTOR(7 downto 0)) and returns the product M=AxB on 8 bits (i.e. STD_LOGIC_VECTOR(7 downto 0) as well). The component is solely combinational and you can use it following the usual VHDL syntax.
We want to extend the CPU ALU to be able to perform a multiplication using this component. This requires: 1) to define a new opcode that corresponds to a “mul” instruction; 2) to modify the processor ALU to add this new functionality; 3) to write an example program to show how to use this new instruction.
Report on the opcode you choose for this new instruction, and explain your choice. Explain how that instruction operates: which are its operands and where the result goes.
Report the modifications that must be made to the processor (provide VHDL code and explanations) to include this new multiplication instruction.
Write a simple example program that uses this new instruction; provide the assembler code and the instruction encoding.
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