Posted: September 17th, 2017

Pedometer Processor


Pedometer Processor
The aim of this assignment is to design and implement the processing required for a pedometer. These are wearable devices that detect footsteps automatically and, from this information, can estimate distances travelled, speed etc.
In a complete system, the input to the processor would come from an accelerometer detecting foot-steps. For the purpose of this exercise, the input will be simulated by one of the push buttons on the Nexys3 FPGA board.
The 7-segment display will be used to feedback information to the user depending on the mode selected by the slide switches. Modes to be implemented are:
• Number of steps taken since start-up (i.e. how many times has the button been pressed) • Distance travelled1 • Average steps-per-minute • Average speed1 All displays should show the requested data as decimal numbers. In order to calculate some of these figures, an estimate of average stride length will be required. You
can measure this for yourself or make an estimate (it is usually around 0.4 times a person’s height). An advanced system would have the facility to input this information so the unit can be personalised for an individual user.
Format of report and submission procedure
The assignment should be written up as a formal report (an appropriate length would be between 7 and 15 pages, not including the appendix). The report should include sections on the following:
• Introduction and overview • Design organisation • Simulation results (including screen shots from simulations that demonstrate your design work-
ing, accompanied by explanations of what is demonstrated by the simulation).
• Synthesis results (including information about how much hardware is used by your design, whether your design could have fitted into a smaller device than the FPGA on the board, and your opinions about which parts of your design consume the most hardware).
• Conclusions
All VHDL code should be included in an appendix. You should also submit an electronic copy of all of your VHDL source files in a .zip file as part of your electronic submission.
Mark scheme
Style, structure and presentation of report
10% Description of system analysis and design process 20% Technical achievements in design, implementation and evaluation 50% Demonstration of good judgement, imagination and creativity 20%
Technical achievement in implementation is based on the quality of your VHDL code. This includes issues such as legibility of code, use of meaningful variable names, good comments, clear structure, and modifiability of the design.
Technical achievement in evaluation is based on the quality of your simulation and synthesis results, how well they have been planned and interpreted.
You may choose any appropriate units for speed and distance but make sure you specify what they are in your report.

The code should be written in VHDL implementing the code on Nexys3 FPGA, Spartan6.

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